This invention relates to the field of electronic signal timing delay devices. More particularly, this invention relates to a new and improved electronic component suitable for use on a printed wiring board and which is capable of adjusting the arrival time of signals in high speed logic systems.
It is well known in the electronic circuitry art that for a digital network to function correctly, certain logic variables must change state at accurately controlled points in time relative to one another. As a consequence, the precise control of signals is an important concern in printed circuit board (PCB) or wiring board (PWB) design. This concern has become especially critical with the advent of high speed digital logic networks.
Time delay lines are used in the electronics industry to adjust the timing of electronic signals. As mentioned, signal timing is often critical for the proper operation of a system, particularly for high speed digital systems. In such systems, an integrated circuit may make decisions based upon two or more input signals. If all required inputs do not arrive at roughly the same time, the decision will be faulty. It is not necessary for the inputs to arrive at exactly the same time, but the arrival window becomes smaller and smaller as the speed of the system increases. As the system becomes more complex, the connections from circuit to circuit become longer and, as a result, the connection length for inputs to an integrated circuit may vary greatly. This variability in input connection length causes the transit time in each connection to vary, resulting in non-uniform arrival times. Since it is not possible to speed up the input signals arriving late, the signals arriving early must be delayed. Thus, a delay line is used to effectively increase the length of a travel of a signal, and therefore its transit time. The delay line's electrical characteristics should be as good as the circuit board on which the signals normally travel. Accordingly, it must have controlled impedance, low losses and minimal cross-talk, and it should not degrade the rise time of the signal.
There is a combination of factors present in a digital system which make it virtually impossible to design and build a digital logic network in which the signal propagation times will meet a precise time specification unless an appropriate compensation device, i.e., delay line, is provided. Moreover, because of inaccuracies in various elements of the logic system, the signal timing can only be set by tuning the network after it has been constructed. These inaccuracies are derived from, for example, gate propagation delays varying from the nominal, different lengths of printed circuit tracks, or uncontrolled delays in connectors and other segments of the digital signal paths.
It will be appreciated that the time it takes for an electronic signal to travel from one point to another in a printed circuit track is a function of, and is determined by, the physical length of the track, the line geometry and the substrate characteristics.
Typically, in high speed logic systems such as those employing Emitter Couple Logic (ECL) or gallium arsenide integrated circuits, the necessary signal timing adjustment is effected by the addition of a printed circuit track having a precise length and loaded in a given signal path. This extra length of printed circuitry track acts as a delay line whereby actual propagration delay is determined by the line length and line configuration or layout. This particular approach at controlling the timing of signals has at least two drawbacks. First, the extra length of circuitry track will use up valuable printed circuit real estate thereby incurring higher costs. Second, the characteristic impedance of the delay line is often difficult to control because of layout and construction problems.
Other time delay devices formed as discrete components and suitable for introduction onto a printed wiring board are also found in the prior art. These devices are generally of two types including lumped parameter and distributed parameter delay lines. Lumped parameter delay lines are made up of individual capacitor and inductor stages in series. The total delay is equal to the sum of the inductances multiplied by the sum of the capacitances. Multiple stages are used to smooth out the impedance as well as reduce the degradation in rise time caused by discrete inductors and capacitors. The higher performance the delay line, the more stages are required. Distributed parameter delay lines have distributed inductance and capacitance. Their performance is better than the lumped parameter type, but they are bulkier and restricted to short delays. It will be appreciated that no matter what construction is utilized, the rise time of the above two delay lines is no better than one nanosecond for even short delays. There are also wide variations in impedance within the components which distort high speed signals.
In U.S. patent application Ser. No. 691,193 to Carey and Brumbaugh, now abandoned, assigned to the assignee hereof, all the contents of which are incorporated herein by reference, a new and improved electronic signal timing delay device is disclosed which is comprised of a microstrip flexible circuit rolled up into a compact strip line form. The benefits of this improved delay line of U.S. patent application Ser. No. 691,193 include excellent impedance control, compact package size, better rise times than found in the prior art and reduced distortion of high speed signals.
While suited for its intended purposes, there is a perceived need to further reduce the size of the electronic signal delay device of U.S. patent application Ser. No. 691,193; and there is also a perceived need to further reduce the cost of manufacturing a signal time delay device of the type disclosed in U.S. patent application Ser. No. 691,193.